Rohit Lorenzo and Saurabh Chaudhury
Keywords: Low power, body biasing, sub-threshold leakage, leakage power, threshold voltage
Abstract: In this paper a body bias technique is proposed for leakage minimization in CMOS VLSI circuits. A gate level body bias controller circuit is designed which dynamically change the threshold voltage of NMOS transistors. When the NMOS transistor is in OFF state, the threshold voltage of transistor is raised by applying reverse body bias through the controller circuit. This reverse body bias raises the threshold voltage of NMOS transistor in the pull down path and hence the sub-threshold leakage current reduces. Here the main focus is to reduce leakage current in NMOS transistors in pull down path because it provides a leakage current path from supply to ground, even in OFF-state. The proposed design is compared with LECTOR technique. Simulation results show that proposed design significantly reduces the power dissipation and gives a low power delay product
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